Accurate Power Analysis of Integrated CMOS Circuits on Gate Level

Thanks are due to my former colleagues of the low power group Gerd Jochens, Lars Kruse and Bernd Timmermann for inspiring discussions. who did numerous simulation runs and part of the implementation of GliPS and OCHATO. I would also like to take the opportunity to thank my colleague Till Winteler for reviewing the manuscript. Microelectronic products are the essential key for products of much higher economic value, which have an increasing impact on everybody's life [VDE96]. The market driven progress of microelectronics in terms of increasing functionality per chip (respectively circuit complexity) and at the same time decreasing its costs is higher than in any other industrial field. The cost reduction per transistor is 25-30% per year throughout semiconductor industry's history [Sema97]. The total maximum number of transistors per chip will increase from 11 million (for MPUs †) in 1998 up to 1.4 billion in 2012 [Sema97] (38% per year) for leading-edge circuits mainly by • decreasing feature sizes (10%-15% per year [Sema97,Bako90 † † ,Inte98 † † † ]) and • increasing die area (6% per year for MPUs (12% for DRAMs) [Sema97] and in the past even 19% per year [Bako90] † †). In conjunction with the technological advances the factory and technology development costs are continuing to escalate [Chat93,Sema97]. These challenges afford a high degree of innovation for technical production and all fields of CAD (Computer Aided Design). On the one hand abstraction is needed to enable handling the large circuit complexities within the design process and on the other hand the number of low-level effects, which significantly influence chip-characteristics (like performance, power consumption and functionality), is increasing. Within this thesis basically two topics are addressed: • accurate digital gate level simulation and • accurate gate level power calculation. To be accurate in both topics, the simulation of the circuit behaviour has to be as close to the actual silicon behaviour as possible. Therefore an adequate delay model is required. Traditional delay models rarely fulfil this demand. Therefore a new delay model has been invented, which is as accurate as fast transistor level simulators (e.g. EPIC's PowerMill † † † †) but features more than one order of magnitude higher simulation performance. The need for accurate simulation is obvious to ensure correct silicon behaviour. Besides this topic the need to fabricate and design ICs for low power has become an important topic within the past few years …